1. Field of the Invention
The field of the invention relates to data processing and in particular to the control of data transfers using a direct memory access controller.
2. Description of the Prior Art
It is known to provide direct memory access controllers, or DMAC for controlling data access between different functional units such as memory and peripherals, without the need to use and therefore interrupt the processor.
A DMA controller may control data transfers between a number of peripherals and a memory. In order to control a particular data transfer a direct memory access controller requires the initial source address of the data, the destination address, the transfer width, e.g. one word i.e. 32 bits and the transfer size, e.g. 3072 bytes. These can be stored in the DMA controller itself. However, if the DMA controller is controlling the memory access of a lot of peripherals then this information needs to be stored for each of these peripherals or channels. This requires a lot of storage and increases the gate count of the DMA controller. A known way of addressing this is to store the control information for each channel in memory and to simply store a pointer to it in the DMA controller. This could be a pointer for each channel, or it could be a pointer to a base address, the control information for the various channels being stored at a known offset from this address. This is fine if the data transfers are continuous linear transfers for each channel, however, if they are disparate such as scatter/gather transfers where data is sent to several destinations or retrieved from several sources then the control data needs to be updated between transfers and this needs to be done by the processor.
One known way of addressing this problem is by the use of linked lists (see for example the PL08x DMAC made by ARM and detailed in the publication to be found at http://www.arm.com/pdfs/DDI0196G_dmac_pl080_r1p3_trm.pdf). In such a set up there is a register in the DMAC for each channel that points to a linked list for that channel. Each linked list controls the transfer of one block of data and then optionally loads another linked list to continue the DMA operation or stops the DMA stream. Thus, the first linked list address defines the first block of data to be transferred, the final address of this block of data storing the next linked list which defines the next block to be transferred and so on, until the next linked list address stores 00, which means that the data transfer can stop. This is an effective way of performing disparate data transfers but does require a register for each channel in the DMA controller to store the linked list pointers.
It would be desirable to have the flexibility to perform disparate data transfers without the need to interrupt the processor and yet maintain a small gate count for the DMA controller.